`timescale 1ns / 1ps
//////////////////////////////////////////////////////////////////////////////////
// Company: 
// Engineer: 
// 
// Create Date: 11/16/2021 09:46:38 PM
// Design Name: 
// Module Name: deathadder
// Project Name: 
// Target Devices: 
// Tool Versions: 
// Description: 
// 
// Dependencies: 
// 
// Revision:
// Revision 0.01 - File Created
// Additional Comments:
// 
//////////////////////////////////////////////////////////////////////////////////


module deathadder(
    input rst_n,
    input en,
    input clk,
    input key_add,
    input [3:0] LD,
    output reg  [3:0] out,
    output reg cout 
    );

    always @(posedge clk or negedge rst_n) begin
        if (!rst_n) begin
            out <= LD;
        end
        else if(en)
        if (key_add && out < 9) begin
            out <= out + 1;
        end
        else if(key_add)
            out <= 0;

    end
    always @(posedge clk) begin
        if (out ==9 && key_add)
            cout <= 1;
        else
            cout <= 0;
    end
endmodule
